This invention relates generally to digital-to-analog converters and more particularly, it relates to a digital-to-analog (D/A) converter network which includes a code-dependent impedance circuit for eliminating offset-induced errors caused by the use of an operational amplifier.
As is generally known, a major problem associated with digital-to-analog converters utilzing an R-2R ladder network is that when operated in a current mode the digital-to-analog converters are sensitive to offset voltage of the operational amplifier used to convert the output current to a voltage. A conventional R-2R ladder network for use with digital-to-analog converters is illustrated in FIG. 1(a) and is composed of equal-valued resistors R arranged in a uniform ladder array. Each section of the ladder array has a leg or rung of a "2R" element, and the connection between the ladder sections has a single "R" element joined between one ladder section and the next ladder section. Another single "R" element is also connected between the last single "R" element and a ground potential so as to complete the ladder array. This type of arrangement provides equal parallel "R" impedance at each node of the ladder array when going from the most significant bit (MSB) to the least significant bit (LSB). Thus, if the resistive elements are of a uniform resistance value a reference current applied to the input at the MSB end will divide equally at each ladder node so that the output current for each successive 2R ladder rung and thus each bit will be one-half of the output current of the previous bit down to the LSB. The uniform resistance value and node current division therefore implies that the voltage drop on each "R" element of the ladder array must decrease by one-half as well for each successive ladder section.
The R-2R ladder network has a first output current summing line 10 to provide an output current IOUT and a second output current summing line 12 to provide an output current IOUTB. Each "2R" leg is connected to respective switches S1, S2, . . . S12 which are controlled by binary bits B.0., B1, . . . B11 of the digital input signal to be converted. Each of the switches S1, S2, . . . S12 is operated to switch current flowing through its respective leg between the first output line 10 and the second output line 12. Normally, the second output line 12 is tied to a reference node or in this case, a ground potential, and the first output line 10 is tied to an output node A. The output impedance Z.sub.OUT as seen across the output lines 10 and 12 varies dependent upon which ones of the "2R" legs are tied to the first output line 10 and which ones of the "2R" legs are tied to the second output line 12. In other words, the magnitude of this output impedance is different for every applied binary code X of the digital input signal. FIG. 2 is a plot of the typical variations of this output impedance Z.sub.OUT as a function of the binary code.
In FIG. 1(b), there is depicted in block form the digital-to-analog converter 8 of FIG. 1(a) whose output lines 10 and 12 are connected to an operational amplifier (op amp) 14 so as to form a D/A converter network. In particular, the first output line 10 is connected to the inverting input of the op amp 14, and the second output line 12 is connected to the non-inverting input of the op amp 14. The output voltage V.sub.OUT at output terminal 15 of the amplifier 14 provides an analog output voltage of the digital-to-analog converter network. The digital-to-analog converter 8 receives a reference current IREF and provides a signal I.sub.SIG on the output line 10. The signal I.sub.SIG is a signal current which is dependent upon the binary code X (i.e., B.0., B1, . . . B11). This signal current constitutes the ideal output of the digital-to-analog converter 8. However, there will be an input dc-offset voltage V.sub.OS ranging from the order of 1 to 10 mV inherent to the op amp when using contemporary NMOS and CMOS technological processes.
As a result, this offset voltage is reflected or induced back into the converter 8 so as to cause an error current I.sub.ERR which is equal to V.sub.OS /Z.sub.OUT, where Z.sub.OUT is the output impedance across the first and second output lines 10 and 12 of the converter 8. Since the output imepedance Z.sub.OUT is dependent upon the binary code X, the error current will thus also be varying as a function of the binary code. Thus, the error current I.sub.ERR is subtracted or reduced from the signal current I.sub.SIG so as to render a resultant current I.sub.RES. Since the error and signal currents cannot be separated, the output voltage V.sub.OUT of the amplifier 14 will be proportional to the resultant current I.sub.RES, thereby causing distortion and adversely affecting the digital-to-analog conversion's accuracy and linearity.
In order to eliminate the problem of error current, there have been attempts in the prior art to make the output impedance Z.sub.OUT very large utilizing digitally controlled current sources. However, this solution suffers from the disadvantage in that it takes very large amounts of chip area where the digital-to-analog converter is more than five or six bits. There have also been proposed in the prior art means for cancelling of the offset voltage V.sub.OS of the op amp such as by utilizing auto-zeroing ciruitry. It has been encountered that this solution is also less than satisfactory since the auto-zeroing circuitry interacts with digital noise so as to degrade the overall operation of the digital-to-analog converter.